Digital Electronics Notes for all units

UNIT I  MINIMIZATION TECHNIQUES AND LOGIC GATES
          
Minimization Techniques: Boolean postulates and laws – De-Morgan‟s Theorem - Principle of Duality - Boolean expression - Minimization of Boolean expressions –– Minterm – Maxterm - Sum of Products (SOP) – Product of Sums (POS) – Karnaugh map Minimization – Don‟t care conditions – Quine - Mc Cluskey method of minimization. Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive–OR and Exclusive–NOR Implementations of Logic Functions using gates, NAND–NOR implementations 

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2 Mark Q & A - Click here to download the full document

UNIT II  COMBINATIONAL CIRCUITS

Design procedure – Half adder – Full Adder – Half Subtractor – Full Subtractor – Parallel binary adder, parallel binary Subtractor – Fast Adder - Carry Look Ahead adder – Serial Adder/Subtractor - BCD adder – Binary Multiplier – Binary Divider - Multiplexer/ Demultiplexer –decoder-encoder–parity checker – parity generators – code converters – Magnitude Comparator. 

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UNIT III   SEQUENTIAL CIRCUITS

Latches, Edge triggered Flip flops SR, JK, T, D and Master slave – Characteristic table and equation, Application table, Synchronous counters, Design of synchronous counters, up/down counter, Modulo–n counter, Decade counters.

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To Download the unit-3 -2 Marks Q&A- Click Here
To Download the unit-3 Important Questions - Click Here
For Full Document of Register - Click Here
For Full Document of Counters- Click Here
For Full Document on Design of Seq Circuits- Click Here


UNIT IV  DESIGN OF SEQUENTIAL CIRCUITS
Register, shift registers, Universal shift register, Ring counters, Classification of sequential circuits: Moore and Mealy, Design of synchronous sequential circuits, state diagram, State table, State minimization, State assignment, Introduction to Hazards: Static, Dynamic.

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Video links for unit-4 - Click Here
To Download the unit-4 - 2 Mark Q&A - Click Here

UNIT V  DIGITAL LOGIC FAMILIES AND PLD

Memories: ROM, PROM, EEPROM, RAM, Programmable Logic Devices: Programmable Logic

Array (PLA), Programmable Array Logic (PAL), Implementation of combinational logic using

PROM , PLA and PAL, Digital logic families: TTL, ECL and CMOS.

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To Download the Notes on PLA, PAL &  Othere PLDs -Click Here
To Download the Unit-5- 2 Mark Q& A - Click Here








To Download the Text Book "Morris Mano M., “Digital Circuits and Logic Design”, Prentice Hall of India, II Edition, 1996" - Click Here


To Download the Last Minute Preparation - Click Here
Digital Electronics ppt for all Chapters - Click Here

To download the "EC 3204 Digital Electronics May june 2013" Question paper - Click Here
To download the "EC 3204 Digital Electronics Nov Dec 2012" Question paper - Click Here
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